A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm
Internet of Things (IoT) represents the internetworking of smart devices embedded with sensors, software, electronics and
network connectivity, enabling them to exchange and collect data through wireless mediums. As IoT devices proliferate,
they bring versatile functionality and real-time data communication, yet remain constrained by low battery power, limited
computation, and susceptibility to unsafe communication channels. Energy consumption has emerged as a prime concern,
with most existing algorithms focusing on minimizing hardware area and maximizing security, rather than optimizing
energy usage. This paper presents the design, implementation, and comparative analysis of the Advanced Encryption
Standard (AES) algorithm on FPGA hardware using Verilog HDL and the Xilinx Vivado toolchain. To enhance security,
a Random Number Generator (RNG) module is integrated to supply randomized encryption keys dynamically. The
proposed lightweight AES implementation meets the dual demand of moderate security and reduced energy consumption
suitable for IoT environments. Results are evaluated in terms of area (LUT utilization), timing delay, and power,
demonstrating the superiority of the hardware-based AES architecture for resource-constrained applications.
Registration ID: IJVRA_702730 Published ID: IJVRA26A3005
"A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm", IJVRA - International Journal of Versatile Research and Analysis (www.IJVRA.org), ISSN:2984-8903, Vol.4, Issue 3, page no.709-718, March-2026, Available :https://ijpub.org/IJVRA/papers/IJVRA26A3005.pdf
Paper Reg. ID: IJVRA_702730
Published Paper Id: IJVRA26A3005
Research Area: Other area not in list
Country: Rangareddy, Telangana, India
ISSN: 2984-8903 | IMPACT FACTOR: 9.12 Calculated By Google Scholar | ESTD YEAR: 2023
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Publisher: IJVRA (IJ Publication) Janvi Wave
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